1 // ***************************************************************************** 2 // IQRF OS memory * 3 // ***************************************************************************** 4 // 5 // Online IQRF OS Reference Guide: http://www.iqrf.org/IQRF-OS-Reference-guide/ 6 // 7 // Copyright (c) MICRORISC s.r.o. 8 // 9 // Intended for: 10 // HW: TR-72D, TR-76D, TR-77D, TR-78D, TR-75D, TR-72G, TR-76G, TR-75G, TR-82G 11 // OS: 4.06D, 4.06G 12 // 13 // File: IQRF-memory.h 14 // Version: v1.00 Revision: 05/08/2022 15 // 16 // Revision history: 17 // v1.01: 05/08/2022 User Flash memory codepages added. 18 // v1.00: 03/06/2022 First release for OS 4.06D and 4.06G. 19 // 20 // ***************************************************************************** 21 22 //****************************************************************************** 23 // Temperature sensor configuration registers 24 //****************************************************************************** 25 typedef struct // Default setting: 0b0000.0100 26 { 27 bit resolution0; 28 bit resolution1; 29 bit powerDownMode; 30 bit skipSetup; 31 } TmpCfg; // For internal usage only 32 33 // ***************************************************************************** 34 uns8 usedBank0[80] @ 0x020; // Do not use this space 35 uns8 usedBank1[80] @ 0x0A0; // Do not use this space 36 uns8 usedBank2[80] @ 0x120; // Do not use this space 37 uns8 usedBank3[80] @ 0x1A0; // Do not use this space 38 uns8 usedBank4[80] @ 0x220; // Do not use this space 39 uns8 usedBank5[80] @ 0x2A0; // Do not use this space 40 uns8 usedBank6[80] @ 0x320; // Do not use this space 41 uns8 usedBank7[80] @ 0x3A0; // Do not use this space 42 uns8 usedBank8[80] @ 0x420; // Do not use this space 43 uns8 usedBank9[80] @ 0x4A0; // Do not use this space 44 uns8 usedBank10[80] @ 0x520; // Do not use this space 45 uns8 usedBank11[32] @ 0x5A0; // Do not use 32B of bank11 (0x5A0 - 0x5BF) 46 // user space: bank11 48B (0x5C0 - 0x5EF) , bank12: 48B (0x620 - 0x64F) @ TR7xD or 80B (0x620 - 0x66F) @ TR7xG 47 #if defined TR7xG || defined TR8xG 48 uns8 usedBank14[80] @ 0x720; // Do not use this space 49 #endif 50 51 #define UserBank_01 11 52 #define UserBank_02 12 53 54 //****************************************************************************** 55 // Dedicated buffers and file registers 56 //****************************************************************************** 57 uns8 bufferINFO[64] @ usedBank6; // Auxiliary buffer, 64B long 58 uns8 bufferCOM[64] @ usedBank7; // Buffer for communication routines, 64B long 59 uns8 bufferAUX[64] @ usedBank8; // Auxiliary buffer, 64B long 60 uns8 bufferRF[64] @ usedBank9; // Buffer for RF routines, 64B long 61 62 uns8 X70[16] @ 0x70; // Register array in shared bank for user application 63 uns8 userReg0 @ X70; // User's register in all banks 64 uns8 userReg1 @ X70[1]; // User's register in all banks 65 uns8 RFmodeByte @ X70[2]; // Current RF mode !!! Read Only !!! 66 uns8 param2 @ X70[3]; // Used as parameter for function calls 67 uns16 param3 @ X70[4]; // Used as parameter for function calls 68 uns16 param4 @ X70[6]; // Used as parameter for function calls 69 uns8 bitmapBitMask @ X70[12]; // Bit mask from addressBitmap function 70 uns8 bitmapByteIndex @ X70[14]; // Byte index from addressBitmap function 71 uns8 userInterface @ X70[15]; // See below !!! Read Only !!! 72 73 // Network params !!! Read Only !!! 74 bank11 uns8 ntwADDR @ usedBank11[0x00]; // Network address 75 bank11 uns8 ntwVRN @ usedBank11[0x01]; // VRN 76 bank11 uns8 ntwZIN @ usedBank11[0x02]; // Zone index 77 bank11 uns8 ntwDID @ usedBank11[0x03]; // Discovery ID 78 bank11 uns8 ntwPVRN @ usedBank11[0x04]; // Parent VRN 79 bank11 uns16 ntwUSERADDRESS @ usedBank11[0x05]; // For internal usage only 80 bank11 uns16 ntwID @ usedBank11[0x07]; // Network identification (NID0/NID1) 81 bank11 uns8 ntwVRNFNZ @ usedBank11[0x09]; // For internal usage only 82 bank11 uns8 ntwCFG @ usedBank11[0x0A]; // Network configuration 83 // 84 bank11 uns8 memoryOffsetFrom @ usedBank11[0x0B]; // Offset for copying buffers 85 bank11 uns8 memoryOffsetTo @ usedBank11[0x0C]; // Offset for copying buffers 86 bank11 uns8 userStatus @ usedBank11[0x0D]; // Register cleared by OS after power-on reset but not after other reset types 87 bank11 uns8 toutRF @ usedBank11[0x0E]; // Timeout for RFRXpacket duration 88 bank11 uns8 RFspeed @ usedBank11[0x0F]; // Current RF speed !!! Read Only !!! 89 bank11 uns8 RFpower @ usedBank11[0x10]; // Current RF power !!! Read Only !!! 90 bank11 uns8 RFchannel @ usedBank11[0x11]; // Current RF channel !!! Read Only !!! 91 bank11 uns8 SPIpacketLength @ usedBank11[0x12]; // SPI packet length !!! Read Only !!! 92 bank11 uns8 lastRSSI @ usedBank11[0x16]; // RSSI of last receipt !!! Read Only !!! 93 bank11 uns8 configFRC @ usedBank11[0x17]; // FRC configuration 94 bank11 uns8 sysReg1 @ usedBank11[0x1B]; // System register 95 // 96 bank11 uns8 responseFRCvalue @ usedBank11[0x1C]; // FRC response value for 2 bits or 1 byte FRC 97 bank11 uns16 responseFRCvalue2B @ usedBank11[0x1C]; // Two bytes FRC response value 98 bank11 uns32 responseFRCvalue4B @ usedBank11[0x1C]; // Four bytes FRC response value (use .low8, .low16, .high16, ... to access this variable at the free CC5X edition) 99 // 100 bank5 uns8 FRCextraTime @ usedBank5[0x49]; // Additional waiting time [ticks] for FRC response 101 bank5 uns8 bondingMask @ usedBank5[0x4E]; // Bonding mask for remote bonding 102 bank5 uns8 bondingCounter @ usedBank5[0x4F]; // Bonding counter for remote bonding 103 // 104 bank3 TmpCfg tmpCfg @ usedBank3[0x49]; // For internal usage only 105 bank3 uns16 CRC16 @ usedBank3[0x4A]; // For internal usage only 106 bank3 uns8 XLPticks @ usedBank3[0x4C]; // Number of ticks remaining to end of XLP packet transmission 107 bank3 uns8 memoryLimit @ usedBank3[0x4D]; // Limit for copying buffers 108 // 109 bank0 uns8 sysReg2 @ usedBank0[0x22]; // System register 110 // 111 #if defined TR7xG || defined TR8xG 112 bank14 uns8 randomValue @ usedBank14[0x00]; // Random value generated by OS 113 #endif 114 115 //****************************************************************************** 116 // After getStatusSPI() in param2 there are information as below 117 //****************************************************************************** 118 bit _SPIRX @ param2.3; // Something received on SPI 119 bit _SPICRCok @ param2.4; // Received SPICRC (last one) was OK 120 121 //****************************************************************************** 122 // After device reset in userReg0 there are information as below 123 //****************************************************************************** 124 bit _BOR @ userReg0.0; // Brown-out Reset flag 125 bit _POR @ userReg0.1; // Power-on Reset flag 126 bit _RI @ userReg0.2; // Reset Instruction Flag 127 bit _PD @ userReg0.3; // Power-down flag 128 bit _TO @ userReg0.4; // Watchdog time-out flag 129 bit _RMCLR @ userReg0.5; // MCLR Reset flag 130 bit _STKUNF @ userReg0.6; // Stack Underflow Reset flag 131 bit _STKOVF @ userReg0.7; // Stack Overflow Reset flag 132 133 //****************************************************************************** 134 // ntwCFG register 135 //****************************************************************************** 136 bit _disabledRouting @ ntwCFG.2; // Routing enabled/disabled !!! Read Only !!! 137 138 //****************************************************************************** 139 // userInterface register 140 //****************************************************************************** 141 bit _enableUserInterrupt @ userInterface.1; // Enable user interrupt 142 bit _wasFRC @ userInterface.2; // FRC packet received !!! Read Only !!! 143 bit _wasRouted @ userInterface.3; // Packet was routed, same as wasRouted() !!! Read Only !!! 144 bit _916MHz @ userInterface.4; // 916 MHz band selected !!! Read Only !!! 145 bit _filterCurrentNetwork @ userInterface.5; // Filtering on !!! Read Only !!! 146 bit _networkTwo @ userInterface.6; // Network 2 selected !!! Read Only !!! 147 bit _networkingMode @ userInterface.7; // Networking selected !!! Read Only !!! 148 149 //****************************************************************************** 150 // System registers 151 //****************************************************************************** 152 bit _systemLEDindication @ sysReg1.2; // Enable system LED indication 153 bit _ignoreForcedRoutingLP @ sysReg1.5; // Disable Forced LP routing 154 // 155 bit _3CHTX @ sysReg2.1; // TX using all 3 service channels 156 bit _eeeError @ sysReg2.3; // External EEPROM communication error indication 157 bit _checkRFcfg_PQT @ sysReg2.5; // Enable preamble quality test for checkRF function 158 159 //****************************************************************************** 160 // Registers dedicated to networking 161 //****************************************************************************** 162 uns8 networkInfo[32] @ usedBank5; 163 164 struct PINfield 165 { 166 bit AUXF1; 167 bit AUXF0; 168 bit SYSPF; 169 bit DPAF; 170 bit CRYPTF; 171 bit ROUTEF; 172 bit ACKF; 173 bit NTWF; 174 175 } PINF @ networkInfo; 176 177 bit _NTWF @ PINF.NTWF; // Networking packet requested 178 bit _ACKF @ PINF.ACKF; // Acknowledgment requested 179 bit _ROUTEF @ PINF.ROUTEF; // Routing requested 180 bit _CRYPTF @ PINF.CRYPTF; // Encryption requested 181 bit _DPAF @ PINF.DPAF; // DPA protocol requested 182 bit _SYSPF @ PINF.SYSPF; // System packet 183 bit _AUXF0 @ PINF.AUXF0; // Reserved for future use 184 bit _AUXF1 @ PINF.AUXF1; // Reserved for future use 185 186 #define _NTWF_MASK 0b1000.0000 187 #define _ACKF_MASK 0b0100.0000 188 #define _ROUTEF_MASK 0b0010.0000 189 #define _CRYPTF_MASK 0b0001.0000 190 #define _DPAF_MASK 0b0000.1000 191 #define _SYSPF_MASK 0b0000.0100 192 #define _AUXF0_MASK 0b0000.0010 193 #define _AUXF1_MASK 0b0000.0001 194 195 uns8 PIN @ networkInfo; // Packet info 196 uns8 DLEN @ networkInfo[1]; // Data length in packet 197 uns8 RX @ networkInfo[3]; // Addressee of packet 198 uns8 TX @ networkInfo[4]; // Direct sender of packet 199 uns8 PID @ networkInfo[7]; // Packet identification 200 uns8 RTOTX @ networkInfo[8]; // Originated sender of packet 201 uns8 RTDEF @ networkInfo[9]; // Routing definition 202 203 uns8 RTHOPS @ networkInfo[10]; // Routing data 0 - number of hops 204 uns8 RTTSLOT @ networkInfo[11]; // Routing data 1 - timeslot length [tick] 205 uns8 RTDID @ networkInfo[12]; // Routing data 2 - Discovery ID (set by OS) 206 uns8 RTAUX @ networkInfo[13]; // Routing data 3 - H byte for 2 byte addressing 207 208 uns8 PNUM @ networkInfo[14]; // DPA - Peripheral number 209 uns8 PCMD @ networkInfo[15]; // DPA - Peripheral command 210 uns8 PPAR @ networkInfo[16]; // DPA - Peripheral parameter 211 212 //****************************************************************************** 213 // Variables for bidirectional user data exchange and MID transfer during prebonding 214 //****************************************************************************** 215 216 // User data passed in/out during (pre)bonding. 217 uns8 hostUserDataToSend[4] @ bufferINFO[22]; // [C/N] > [N] before (pre)bonding function 218 uns8 nodeUserDataToSend[4] @ bufferINFO[22]; // [N] > [C/N] before (pre)bonding function 219 uns8 hostUserDataReceived[4] @ bufferINFO[22]; // [C/N] > [N] after (pre)bonding function 220 uns8 nodeUserDataReceived[4] @ bufferRF[6]; // [N] > [C/N] after (pre)bonding function 221 222 uns8 BondingNodeMID[4] @ bufferRF[0]; // MID of the bond requesting node in the received system packet, before optional call of prebondNode(), or 223 // MID of prebonded Node to be authorized by nodeAuthorization(address). 224 225 //****************************************************************************** 226 // FRC variables 227 //****************************************************************************** 228 // configFRC register 229 bit _selectiveFRCmode @ configFRC.0; // Enables selective FRC 230 bit _2ByteFRCmode @ configFRC.1; // Enables two byte FRC 231 bit _4ByteFRCmode @ configFRC.2; // Enables four byte FRC 232 bit _virtualFRCmode @ configFRC.7; // Enables virtual FRC 233 bit _localFRC @ sysReg2.0; // Enables local FRC 234 235 // Variables for bidirectional user data exchange during FRC 236 uns8 DataInSendFRC[30] @ bufferRF[32];// User data passed with FRC, filled-in before calling sendFRC(). 237 uns8 DataOutBeforeResponseFRC[30] @ bufferRF[32];// User data obtained after FRC receiving, formerly passed via DataInSendFRC. 238 uns8 AddressedNodesBeforeResponseFRC[30] @ bufferRF[0]; // Bitmap of Nodes the FRC wants to receive FRC value from 239 240 bit _SelectiveFRC @ bufferRF[30].0; // Selective FRC indicator on Node side 241 bit _2ByteFRC @ bufferRF[30].1; // Two byte FRC indicator on Node side 242 bit _4ByteFRC @ bufferRF[30].2; // Four byte FRC indicator on Node side 243 bit _virtualFRC @ bufferRF[30].7; // Virtual FRC indicator on Node side 244 245 //****************************************************************************** 246 // TR module info 247 //****************************************************************************** 248 // Module info structure available at bufferINFO after calling moduleInfo(); 249 typedef struct 250 { 251 uns8 MID[4]; 252 uns8 OsVersion; 253 uns8 TrType; 254 uns16 OsBuild; 255 } TModuleInfo; 256 257 TModuleInfo ModuleInfo @ bufferINFO; 258 259 //****************************************************************************** 260 // Constants 261 //****************************************************************************** 262 #define __EEESTART 0x0200 // Virtual begin of external EEPROM 263 264 #define __EESTART 0xF000 // Begin of internal EEPROM 265 #define __EEAPPINFO 0xF0A0 // EEPROM user's application data, 32B 266 267 #define __EXTENDED_FLASH 0x2C00 // Begin of extended Flash memory 268 #define __LICENSED_FLASH __EXTENDED_FLASH 269 #define __EXTENDED_FLASH_NEXT_PAGE 0x3000 // Next page of extended Flash memory 270 #define __USER_FLASH_PAGE_6 0x3000 // Next page of extended Flash memory 271 #define __LICENSED_FLASH_NEXT_PAGE __EXTENDED_FLASH_NEXT_PAGE 272 #define __MAX_LICENSED_FLASH_ADDRESS 0x37BF // Maximum address at licensed Flash memory 273 274 #if defined TR7xD 275 #define __USER_INTERRUPT 0x3F00 // User interrupt address 276 #define __MAX_FLASH_ADDRESS 0x3FFF // Maximum Flash memory address 277 #elif defined TR7xG || defined TR8xG 278 #define __USER_INTERRUPT 0x4F00 // User interrupt address 279 #define __USER_FLASH_PAGE_8 0x4000 280 #define __USER_FLASH_PAGE_9 0x4800 281 #define __MAX_USER_FLASH_ADDRESS 0x4FFF // Maximum user Flash memory address 282 #define __MAX_FLASH_ADDRESS 0x7FFF // Maximum Flash memory address 283 #else 284 #error Unsupported TR module type. 285 #endif 286 287 #ifndef __APPLICATION_ADDRESS 288 #define __APPLICATION_ADDRESS 0x3A00 // Begin of user application Flash memory 289 #endif 290 291 #define __FRCOMMAND 0x0D // FRC command 292 #define __FRCOMMANDADV 0x0C // Advanced FRC command 293 294 //****************************************************************************** 295 // I/O definitions 296 //****************************************************************************** 297 #define _SDO LATC.5 // SPI SDO (output) 298 #define _SDI PORTC.4 // SPI SDI (input) 299 #define _SCK PORTC.3 // SPI SCK (input) 300 #define _SS PORTA.5 // SPI SS (input) 301 #define _LEDR LATA.2 // Red LED (output) 302 #define _LEDG LATB.7 // Green LED (output) 303 304 // Ext. EEPROM & temper. sensor supply voltage control (output) 305 #if defined TR7xD 306 #define _PWRT LATA.3 307 #elif defined TR7xG || defined TR8xG 308 #define _PWRT LATE.0 309 #else 310 #error Unsupported TR module type. 311 #endif 312 313 #if defined TR72D || defined TR72G || defined TR82G 314 #define _C1_IN PORTA.0 // C1 as input 315 #define _C1_OUT LATA.0 // C1 as output 316 #define _C1_TRIS TRISA.0 // C1 direction 317 318 #define _C2_IN PORTC.2 // C2 as input 319 #define _C2_OUT LATC.2 // C2 as output 320 #define _C2_TRIS TRISC.2 // C2 direction 321 322 #define _C5_IN PORTA.5 // C5 (SS) as input 323 #define _C5_OUT LATA.5 // C5 (SS) as output 324 #define _C5_TRIS TRISA.5 // C5 (SS) direction 325 326 #define _C6_IN PORTC.3 // C6 (SCK) as input 327 #define _C6_OUT LATC.3 // C6 (SCK) as output 328 #define _C6_TRIS TRISC.3 // C6 (SCK) direction 329 330 #define _C7_IN PORTC.4 // C7 (SDI) as input 331 #define _C7_OUT LATC.4 // C7 (SDI) as output 332 #define _C7_TRIS TRISC.4 // C7 (SDI) direction 333 334 #define _C8_IN PORTC.5 // C8 (SDO) as input 335 #define _C8_OUT LATC.5 // C8 (SDO) as output 336 #define _C8_TRIS TRISC.5 // C8 (SDO) direction 337 338 #elif defined TR76D || defined TR77D || defined TR76G 339 #define _WAKEUP PORTB.4 // Wake-up (Q12) (input) 340 341 #define _Q4_IN PORTC.6 // Q4 as input 342 #define _Q4_OUT LATC.6 // Q4 as output 343 #define _Q4_TRIS TRISC.6 // Q4 direction 344 345 #define _Q5_IN PORTC.7 // Q5 as input 346 #define _Q5_OUT LATC.7 // Q5 as output 347 #define _Q5_TRIS TRISC.7 // Q5 direction 348 349 #define _Q6_IN PORTC.3 // Q6 (SCK) as input 350 #define _Q6_OUT LATC.3 // Q6 (SCK) as output 351 #define _Q6_TRIS TRISC.3 // Q6 (SCK) direction 352 353 #define _Q7_IN PORTC.4 // Q7 (SDI) as input 354 #define _Q7_OUT LATC.4 // Q7 (SDI) as output 355 #define _Q7_TRIS TRISC.4 // Q7 (SDI) direction 356 357 #define _Q8_IN PORTC.5 // Q8 (SDO) as input 358 #define _Q8_OUT LATC.5 // Q8 (SDO) as output 359 #define _Q8_TRIS TRISC.5 // Q8 (SDO) direction 360 361 #define _Q9_IN PORTA.5 // Q9 (SS) as input 362 #define _Q9_OUT LATA.5 // Q9 (SS) as output 363 #define _Q9_TRIS TRISA.5 // Q9 (SS) direction 364 365 #define _Q10_IN PORTB.7 // Q10 (LEDG) as input 366 #define _Q10_OUT LATB.7 // Q10 (LEDG) as output 367 #define _Q10_TRIS TRISB.7 // Q10 (LEDG) direction 368 369 #define _Q11_IN PORTA.2 // Q11 (LEDR) as input 370 #define _Q11_OUT LATA.2 // Q11 (LEDR) as output 371 #define _Q11_TRIS TRISA.2 // Q11 (LEDR) direction 372 373 #define _Q12_IN PORTB.4 // Q12 (wake-up) as input 374 #define _Q12_OUT LATB.4 // Q12 (wake-up) as output 375 #define _Q12_TRIS TRISB.4 // Q12 (wake-up) direction 376 377 #define _Q13_IN PORTE.3 // Q13 as input (input only) 378 #define _Q13_TRIS TRISE.3 // Q13 direction 379 380 #define _Q14_IN PORTA.0 // Q14 as input 381 #define _Q14_OUT LATA.0 // Q14 as output 382 #define _Q14_TRIS TRISA.0 // Q14 direction 383 384 #define _Q15_IN PORTC.2 // Q15 as input 385 #define _Q15_OUT LATC.2 // Q15 as output 386 #define _Q15_TRIS TRISC.2 // Q15 direction 387 388 #elif defined TR78D 389 #define _Q3_IN PORTC.4 // Q3 (SDI) as input 390 #define _Q3_OUT LATC.4 // Q3 (SDI) as output 391 #define _Q3_TRIS TRISC.4 // Q3 (SDI) direction 392 393 #define _Q4_IN PORTC.5 // Q4 (SDO) as input 394 #define _Q4_OUT LATC.5 // Q4 (SDO) as output 395 #define _Q4_TRIS TRISC.5 // Q4 (SDO) direction 396 397 #define _Q5_IN PORTA.5 // Q5 (SS) as input 398 #define _Q5_OUT LATA.5 // Q5 (SS) as output 399 #define _Q5_TRIS TRISA.5 // Q5 (SS) direction 400 401 #define _Q6_IN PORTC.3 // Q6 (SCK) as input 402 #define _Q6_OUT LATC.3 // Q6 (SCK) as output 403 #define _Q6_TRIS TRISC.3 // Q6 (SCK) direction 404 405 #elif defined TR75D || defined TR75G 406 #define _WAKEUP PORTB.4 // Wake-up (Q2) (input) 407 408 #define _Q2_IN PORTB.4 // Q2 (wake-up) as input 409 #define _Q2_OUT LATB.4 // Q2 (wake-up) as output 410 #define _Q2_TRIS TRISB.4 // Q2 (wake-up) direction 411 412 #define _Q3_IN PORTA.5 // Q3 (SS) as input 413 #define _Q3_OUT LATA.5 // Q3 (SS) as output 414 #define _Q3_TRIS TRISA.5 // Q3 (SS) direction 415 416 #define _Q4_IN PORTC.5 // Q4 (SDO) as input 417 #define _Q4_OUT LATC.5 // Q4 (SDO) as output 418 #define _Q4_TRIS TRISC.5 // Q4 (SDO) direction 419 420 #define _Q5_IN PORTC.4 // Q5 (SDI) as input 421 #define _Q5_OUT LATC.4 // Q5 (SDI) as output 422 #define _Q5_TRIS TRISC.4 // Q5 (SDI) direction 423 424 #define _Q6_IN PORTC.3 // Q6 (SCK) as input 425 #define _Q6_OUT LATC.3 // Q6 (SCK) as output 426 #define _Q6_TRIS TRISC.3 // Q6 (SCK) direction 427 428 #define _Q8_IN PORTE.3 // Q8 as input (input only) 429 #define _Q8_TRIS TRISE.3 // Q8 direction 430 431 #define _Q9_IN PORTA.0 // Q9 as input 432 #define _Q9_OUT LATA.0 // Q9 as output 433 #define _Q9_TRIS TRISA.0 // Q9 direction 434 435 #define _Q10_IN PORTC.2 // Q10 as input 436 #define _Q10_OUT LATC.2 // Q10 as output 437 #define _Q10_TRIS TRISC.2 // Q10 direction 438 439 #define _Q11_IN PORTC.7 // Q11 as input 440 #define _Q11_OUT LATC.7 // Q11 as output 441 #define _Q11_TRIS TRISC.7 // Q11 direction 442 443 #define _Q12_IN PORTC.6 // Q12 as input 444 #define _Q12_OUT LATC.6 // Q12 as output 445 #define _Q12_TRIS TRISC.6 // Q12 direction 446 447 #else 448 #error IQRF-memory.h does not correspond to selected TR module type. 449 #endif 450 //****************************************************************************** 451 #pragma rambank = UserBank_01 // User's registers will be allocated in bank11