1 // *********************************************************************
    2 //                               IQRF OS macros                        *
    3 // *********************************************************************
    4 // Just for easier life (better mnemonic and compatibility with older
    5 // versions only).
    6 //
    7 // Online IQRF OS Reference Guide: http://www.iqrf.org/IQRF-OS-Reference-guide/
    8 //
    9 // Copyright (c) MICRORISC s.r.o.
   10 //
   11 // Intended for:
   12 //   HW: TR-72D, TR-76D, TR-77D, TR-78D, TR-75D, TR-72G, TR-76G, TR-82G
   13 //   OS: 4.06D, 4.06G
   14 //
   15 // File:    IQRF-macros.h
   16 // Version: v1.00                                   Revision: 25/02/2022
   17 //
   18 // Revision history:
   19 //   v1.00: 25/02/2022  First release for OS 4.06D and 4.06G.
   20 //
   21 // *********************************************************************
   22 
   23 #define TRUE            1
   24 #define FALSE           0
   25 
   26 #define F_OSC           16000000    // 16 MHz MCU clock
   27 
   28 #define buttonPressed   (!PORTB.4)  // Button on DK-EVAL-04x
   29 #define TX_POWER_MAX    7
   30 #define EEE_BLOCK_SIZE  64          // External EEPROM data block size
   31 
   32 #define setTXpower(level)   setRFpower(level)
   33 #define prebondNode()       prebondNodeAtNode()
   34 
   35 // --- setRFmode(mode) ---
   36 #define _RX_STD         0x00        // RX mode STD
   37 #define _RX_LP          0x01        // RX mode LP
   38 #define _RX_XLP         0x02        // RX mode XLP
   39 #define _RLPMAT         0x04        // LP/XLP RX asynchronous termination
   40 #define _TX_STD         0x00        // TX mode STD
   41 #define _TX_LP          0x10        // TX mode LP
   42 #define _TX_XLP         0x20        // TX mode XLP
   43 #define _WPE            0x40        // Wait Packet End
   44 #define _STDL           0x80        // Prolongs preamble for STD TX mode
   45 
   46 // --- Reset ---
   47 #define reset()         softReset()
   48 
   49 // --- Sleep with wake-up on pin change ---
   50 // Remarks: FSR1 register is destroyed
   51 #define sleepWOC()                          /* Wake-up on both rising and falling edge*/            \
   52     do {                                                                                            \
   53         GIE = 0;                            /* Global interrupt disabled*/                          \
   54         IOCBP.4 = 1;                        /* Positive edge enabled (clear if not required)*/      \
   55                                             /* Negative edge enabled. */                            \
   56 #if defined TR7xD                                                                                   \
   57         FSR1 = &IOCBN;                                                                              \
   58         setINDF1( IOCBN | 0x10 );                                                                   \
   59 #else                                                                                               \
   60         IOCBN.4 = 1;                                                                              \
   61 #endif                                                                                              \
   62                                                                                                     \
   63         IOCIE = 1;                          /* Interrupt on change enabled*/                        \
   64         GIE = 1;                            /* Global interrupt enabled*/                           \
   65         setWDToff();                        /* Watchdog disabled*/                                  \
   66         iqrfSleep();                        /* Sleep*/                                              \
   67         GIE = 0;                                                                                    \
   68                                             /* Negative edge disabled (IOCBN.4)*/                   \
   69 #if defined TR7xD                                                                                   \
   70         FSR1 = &IOCBN;                                                                              \
   71         setINDF1(IOCBN & ~0x10);                                                                    \
   72 #else                                                                                               \
   73         IOCBN.4 = 0;                                                                             \
   74 #endif                                                                                              \
   75         IOCBP.4 = 0;                        /* Positive edge disabled*/                             \
   76         GIE = 1;                                                                                    \
   77     } while (0)
   78 
   79 // --- Watchdog Timer ---
   80 #define setWDTon()        _WDTCON.0 = 1             // WDT on
   81 #define setWDToff()       _WDTCON.0 = 0             // WDT off
   82 
   83 #define WDTCON_1ms        0b00000.1                 // WDT on, timeout 1 ms
   84 #define WDTCON_2ms        0b00001.1                 // WDT on, timeout 2 ms
   85 #define WDTCON_4ms        0b00010.1                 // WDT on, timeout 4 ms
   86 #define WDTCON_8ms        0b00011.1                 // WDT on, timeout 8 ms
   87 #define WDTCON_16ms       0b00100.1                 // WDT on, timeout 16 ms
   88 #define WDTCON_32ms       0b00101.1                 // WDT on, timeout 32 ms
   89 #define WDTCON_64ms       0b00110.1                 // WDT on, timeout 64 ms
   90 #define WDTCON_128ms      0b00111.1                 // WDT on, timeout 128 ms
   91 #define WDTCON_256ms      0b01000.1                 // WDT on, timeout 256 ms
   92 #define WDTCON_512ms      0b01001.1                 // WDT on, timeout 512 ms
   93 #define WDTCON_1s         0b01010.1                 // WDT on, timeout 1 s
   94 #define WDTCON_2s         0b01011.1                 // WDT on, timeout 2 s
   95 #define WDTCON_4s         0b01100.1                 // WDT on, timeout 4 s
   96 #define WDTCON_8s         0b01101.1                 // WDT on, timeout 8 s
   97 #define WDTCON_16s        0b01110.1                 // WDT on, timeout 16 s
   98 #define WDTCON_32s        0b01111.1                 // WDT on, timeout 32 s
   99 #define WDTCON_64s        0b10000.1                 // WDT on, timeout 64 s
  100 #define WDTCON_128s       0b10001.1                 // WDT on, timeout 128 s
  101 #define WDTCON_256s       0b10010.1                 // WDT on, timeout 256 s
  102 
  103 #define setWDTon_1ms()    _WDTCON = WDTCON_1ms      // WDT on, timeout 1 ms
  104 #define setWDTon_2ms()    _WDTCON = WDTCON_2ms      // WDT on, timeout 2 ms
  105 #define setWDTon_4ms()    _WDTCON = WDTCON_4ms      // WDT on, timeout 4 ms
  106 #define setWDTon_8ms()    _WDTCON = WDTCON_8ms      // WDT on, timeout 8 ms
  107 #define setWDTon_16ms()   _WDTCON = WDTCON_16ms     // WDT on, timeout 16 ms
  108 #define setWDTon_32ms()   _WDTCON = WDTCON_32ms     // WDT on, timeout 32 ms
  109 #define setWDTon_64ms()   _WDTCON = WDTCON_64ms     // WDT on, timeout 64 ms
  110 #define setWDTon_128ms()  _WDTCON = WDTCON_128ms    // WDT on, timeout 128 ms
  111 #define setWDTon_256ms()  _WDTCON = WDTCON_256ms    // WDT on, timeout 256 ms
  112 #define setWDTon_512ms()  _WDTCON = WDTCON_512ms    // WDT on, timeout 512 ms
  113 #define setWDTon_1s()     _WDTCON = WDTCON_1s       // WDT on, timeout 1 s
  114 #define setWDTon_2s()     _WDTCON = WDTCON_2s       // WDT on, timeout 2 s
  115 #define setWDTon_4s()     _WDTCON = WDTCON_4s       // WDT on, timeout 4 s
  116 #define setWDTon_8s()     _WDTCON = WDTCON_8s       // WDT on, timeout 8 s
  117 #define setWDTon_16s()    _WDTCON = WDTCON_16s      // WDT on, timeout 16 s
  118 #define setWDTon_32s()    _WDTCON = WDTCON_32s      // WDT on, timeout 32 s
  119 #define setWDTon_64s()    _WDTCON = WDTCON_64s      // WDT on, timeout 64 s
  120 #define setWDTon_128s()   _WDTCON = WDTCON_128s     // WDT on, timeout 128 s
  121 #define setWDTon_256s()   _WDTCON = WDTCON_256s     // WDT on, timeout 256 s
  122 
  123 // --- Debug with breakpoint number ---
  124 // uns8 wValue: breakpoint number displayed in IQRF IDE
  125 #define debugW(wValue)  \
  126     do {                \
  127         W = wValue;     \
  128         debug();        \
  129     } while (0)
  130 
  131 #define breakpoint(wValue)  debugW(wValue)
  132 
  133 // --- Brown-Out Reset ---
  134 #if defined TR7xD
  135     #define setBORon()      writeToRAM(&BORCON, 0x80)   // BOR on
  136     #define setBORoff()     writeToRAM(&BORCON, 0x00)   // BOR off
  137 #endif
  138 
  139 // --- setupRFPGM(parameter) ---
  140 #define _DUAL_CHANNEL       0x03        // RFPGM dual channel receiving
  141 #define _LP_MODE            0x04        // RFPGM low power mode receiving
  142 #define _ENABLE_ON_RESET    0x10        // RFPGM invoking by reset
  143 #define _TIME_TERMINATE     0x40        // RFPGM auto termination after ~1 min
  144 #define _PIN_TERMINATE      0x80        // RFPGM termination by MCU pins
  145 
  146 // --- external EEPROM & temperature sensor power control ---
  147 #define eEEPROM_TempSensorOn()  _PWRT = 1
  148 #define eEEPROM_TempSensorOff() _PWRT = 0
  149 
  150 // --- Interrupt on change flags control ---
  151 #define clearIOCF()         IOCBF.4 = 0                         // Clear interrupt on change flag.
  152 #if defined TR7xD
  153     #define clearIOCBN()    writeToRAM(&IOCBN, IOCBN & ~0x10)   // Clear negative edge flag. This bit (IOCBN.4) can not be accessed directly due to OS restriction.
  154     #define setIOCBN()      writeToRAM(&IOCBN, IOCBN | 0x10)    // Negative edge active. This bit (IOCBN.4) can not be accessed directly due to OS restriction.
  155 #else
  156     #define clearIOCBN()    IOCBN.4 = 0                         // Clear negative edge flag.
  157     #define setIOCBN()      IOCBN.4 = 1                         // Negative edge active.
  158 #endif
  159 
  160 // --- FRC Response time ---
  161 #define _FRC_RESPONSE_TIME_40_MS        0b0.000.0000  // 40 ms
  162 #define _FRC_RESPONSE_TIME_360_MS       0b0.001.0000  // 360 ms
  163 #define _FRC_RESPONSE_TIME_680_MS       0b0.010.0000  // 680 ms
  164 #define _FRC_RESPONSE_TIME_1320_MS      0b0.011.0000  // 1320 ms
  165 #define _FRC_RESPONSE_TIME_2600_MS      0b0.100.0000  // 2600 ms
  166 #define _FRC_RESPONSE_TIME_5160_MS      0b0.101.0000  // 5160 ms
  167 #define _FRC_RESPONSE_TIME_10280_MS     0b0.110.0000  // 10280 ms
  168 #define _FRC_RESPONSE_TIME_20520_MS     0b0.111.0000  // 20520 ms
  169 
  170 // --- FRC offline mode to set before sendFRC() is called ---
  171 #define _FRC_OFFLINE_MODE               0b0000.1.000
  172 
  173 // Only value ORed from the predefined constants ( FRC_RESPONSE_TIME_??? and/or _FRC_OFFLINE_MODE ) above can be used as a parameter "params"
  174 #define setFRCparams( params )                                                             \
  175     do {                                                                                   \
  176         configFRC &= ~( _FRC_RESPONSE_TIME_20520_MS | _FRC_OFFLINE_MODE );                 \
  177         configFRC |= ( ( params ) & ( _FRC_RESPONSE_TIME_20520_MS | _FRC_OFFLINE_MODE ) ); \
  178     } while (0)
  179 
  180 #define getFRCparams()          ( configFRC & ( _FRC_RESPONSE_TIME_20520_MS | _FRC_OFFLINE_MODE ) )
  181 
  182 // --- Copy Application data from EEPROM to bufferINFO ---
  183 #define appInfo()               eeReadData((__EEAPPINFO - __EESTART), 32)
  184 
  185 // --- Write one byte to specified location in RAM ---
  186 #define writeToRAM(address, value)  \
  187     do {                            \
  188         FSR0=address;               \
  189         setINDF0(value);            \
  190     } while(0)
  191 
  192 // --- Macros relating to setFSRs() function ---
  193 #define setFSR01(fsr0, fsr1)    setFSRs( (fsr0) + ( ((uns8)(fsr1)) << 4 ) )
  194 #define setFSR0(fsr0)           setFSR01( fsr0, _FSR_NONE )
  195 #define setFSR1(fsr1)           setFSR01( _FSR_NONE, fsr1 )
  196 
  197 #define _FSR_NONE               0x00    // Set FSR to no buffer
  198 #define _FSR_NINFO              0x01    // Set FSR to networkInfo
  199 #define _FSR_INFO               0x02    // Set FSR to bufferINFO
  200 #define _FSR_COM                0x03    // Set FSR to bufferCOM
  201 #define _FSR_AUX                0x04    // Set FSR to bufferAUX
  202 #define _FSR_RF                 0x05    // Set FSR to bufferRF
  203 #define _FSR_ntwADDR            0x07    // Set FSR to ntwADDR (bank 11)
  204 
  205 // --- Service channels ---
  206 #define SERVICE_CHANNELS_COUNT  3
  207 
  208 // --- LED control ---
  209 #define toggleLEDR()                                                                      \
  210 #warning Do not combine direct access to the LEDs with calling the IQRF OS LED functions. \
  211     do { _LEDR ^= 1; } while ( 0 )
  212 
  213 #define toggleLEDG()                                                                      \
  214 #warning Do not combine direct access to the LEDs with calling the IQRF OS LED functions. \
  215     do { _LEDG ^= 1; } while ( 0 )
  216 
  217 // --- PPS control ---
  218 #if defined TR7xG || defined TR8xG
  219     #define unlockPPS()     \
  220         do {                \
  221             GIE = 0;        \
  222             PPSLOCK = 0x55; \
  223             PPSLOCK = 0xAA; \
  224             PPSLOCKED = 0;  \
  225         } while(0)
  226             
  227     #define lockPPS()       \
  228         do {                \
  229             PPSLOCK = 0x55; \
  230             PPSLOCK = 0xAA; \
  231             PPSLOCKED = 1;  \
  232             GIE = 1;        \
  233         } while(0)
  234 #endif
  235 
  236 // --- Macros relating to registers that can not be written directly due to OS restriction ---
  237 #if defined TR7xG || defined TR8xG
  238     #define setADPCH(value)     writeToRAM(&ADPCH, value)       // ADPCH
  239     #define setTX1STA(value)    writeToRAM(&TX1STA, value)      // TX1STA
  240     #define setBAUD1CON(value)  writeToRAM(&BAUD1CON, value)    // BAUD1CON
  241     #define setCCPTMRS0(value)  writeToRAM(&CCPTMRS0, value)    // CCPTMRS0
  242 #endif
  243 
  244 // *********************************************************************