1 // ********************************************************************* 2 // IQRF OS macros * 3 // ********************************************************************* 4 // Just for easier life (better mnemonic and compatibility with older 5 // versions only). 6 // 7 // Online IQRF OS Reference Guide: http://www.iqrf.org/IQRF-OS-Reference-guide/ 8 // 9 // Copyright (c) MICRORISC s.r.o. 10 // 11 // Intended for: 12 // HW: TR-72D, TR-76D, TR-77D, TR-78D, TR-75D, TR-72G, TR-76G 13 // OS: 4.05D, 4.05G 14 // 15 // File: IQRF-macros.h 16 // Version: v1.00 Revision: 21/07/2021 17 // 18 // Revision history: 19 // v1.00: 21/07/2021 First release for OS 4.05D and 4.05G. 20 // 21 // ********************************************************************* 22 23 /* ToDo macros for unaccessible registers at G modules? 24 * TX1STA 25 * BAUD1CON 26 * ADPCH 27 * CCP5CON 28 * CCP5CAP 29 * (PIE8) 30 * (T6AINPPS) 31 */ 32 33 #define TRUE 1 34 #define FALSE 0 35 36 #define F_OSC 16000000 // 16 MHz MCU clock 37 38 #define buttonPressed (!PORTB.4) // Button on DK-EVAL-04x 39 #define TX_POWER_MAX 7 40 #define EEE_BLOCK_SIZE 64 // External EEPROM data block size 41 42 #define setTXpower(level) setRFpower(level) 43 #define prebondNode() prebondNodeAtNode() 44 45 // --- setRFmode(mode) --- 46 #define _RX_STD 0x00 // RX mode STD 47 #define _RX_LP 0x01 // RX mode LP 48 #define _RX_XLP 0x02 // RX mode XLP 49 #define _RLPMAT 0x04 // LP/XLP RX asynchronous termination 50 #define _TX_STD 0x00 // TX mode STD 51 #define _TX_LP 0x10 // TX mode LP 52 #define _TX_XLP 0x20 // TX mode XLP 53 #define _WPE 0x40 // Wait Packet End 54 #define _STDL 0x80 // Prolongs preamble for STD TX mode 55 56 // --- Reset --- 57 #define reset() softReset() 58 59 // --- Sleep with wake-up on pin change --- 60 // Remarks: FSR1 register is destroyed 61 #define sleepWOC() /* Wake-up on both rising and falling edge*/ \ 62 do { \ 63 GIE = 0; /* Global interrupt disabled*/ \ 64 IOCBP.4 = 1; /* Positive edge enabled (clear if not required)*/ \ 65 /* Negative edge enabled. */ \ 66 #if defined TR7xD \ 67 FSR1 = &IOCBN; \ 68 setINDF1( IOCBN | 0x10 ); \ 69 #else \ 70 IOCBN.4 = 1; \ 71 #endif \ 72 \ 73 IOCIE = 1; /* Interrupt on change enabled*/ \ 74 GIE = 1; /* Global interrupt enabled*/ \ 75 setWDToff(); /* Watchdog disabled*/ \ 76 iqrfSleep(); /* Sleep*/ \ 77 GIE = 0; \ 78 /* Negative edge disabled (IOCBN.4)*/ \ 79 #if defined TR7xD \ 80 FSR1 = &IOCBN; \ 81 setINDF1(IOCBN & ~0x10); \ 82 #else \ 83 IOCBN.4 = 0; \ 84 #endif \ 85 IOCBP.4 = 0; /* Positive edge disabled*/ \ 86 GIE = 1; \ 87 } while (0) 88 89 // --- Watchdog Timer --- 90 #define setWDTon() _WDTCON.0 = 1 // WDT on 91 #define setWDToff() _WDTCON.0 = 0 // WDT off 92 93 #define WDTCON_1ms 0b00000.1 // WDT on, timeout 1 ms 94 #define WDTCON_2ms 0b00001.1 // WDT on, timeout 2 ms 95 #define WDTCON_4ms 0b00010.1 // WDT on, timeout 4 ms 96 #define WDTCON_8ms 0b00011.1 // WDT on, timeout 8 ms 97 #define WDTCON_16ms 0b00100.1 // WDT on, timeout 16 ms 98 #define WDTCON_32ms 0b00101.1 // WDT on, timeout 32 ms 99 #define WDTCON_64ms 0b00110.1 // WDT on, timeout 64 ms 100 #define WDTCON_128ms 0b00111.1 // WDT on, timeout 128 ms 101 #define WDTCON_256ms 0b01000.1 // WDT on, timeout 256 ms 102 #define WDTCON_512ms 0b01001.1 // WDT on, timeout 512 ms 103 #define WDTCON_1s 0b01010.1 // WDT on, timeout 1 s 104 #define WDTCON_2s 0b01011.1 // WDT on, timeout 2 s 105 #define WDTCON_4s 0b01100.1 // WDT on, timeout 4 s 106 #define WDTCON_8s 0b01101.1 // WDT on, timeout 8 s 107 #define WDTCON_16s 0b01110.1 // WDT on, timeout 16 s 108 #define WDTCON_32s 0b01111.1 // WDT on, timeout 32 s 109 #define WDTCON_64s 0b10000.1 // WDT on, timeout 64 s 110 #define WDTCON_128s 0b10001.1 // WDT on, timeout 128 s 111 #define WDTCON_256s 0b10010.1 // WDT on, timeout 256 s 112 113 #define setWDTon_1ms() _WDTCON = WDTCON_1ms // WDT on, timeout 1 ms 114 #define setWDTon_2ms() _WDTCON = WDTCON_2ms // WDT on, timeout 2 ms 115 #define setWDTon_4ms() _WDTCON = WDTCON_4ms // WDT on, timeout 4 ms 116 #define setWDTon_8ms() _WDTCON = WDTCON_8ms // WDT on, timeout 8 ms 117 #define setWDTon_16ms() _WDTCON = WDTCON_16ms // WDT on, timeout 16 ms 118 #define setWDTon_32ms() _WDTCON = WDTCON_32ms // WDT on, timeout 32 ms 119 #define setWDTon_64ms() _WDTCON = WDTCON_64ms // WDT on, timeout 64 ms 120 #define setWDTon_128ms() _WDTCON = WDTCON_128ms // WDT on, timeout 128 ms 121 #define setWDTon_256ms() _WDTCON = WDTCON_256ms // WDT on, timeout 256 ms 122 #define setWDTon_512ms() _WDTCON = WDTCON_512ms // WDT on, timeout 512 ms 123 #define setWDTon_1s() _WDTCON = WDTCON_1s // WDT on, timeout 1 s 124 #define setWDTon_2s() _WDTCON = WDTCON_2s // WDT on, timeout 2 s 125 #define setWDTon_4s() _WDTCON = WDTCON_4s // WDT on, timeout 4 s 126 #define setWDTon_8s() _WDTCON = WDTCON_8s // WDT on, timeout 8 s 127 #define setWDTon_16s() _WDTCON = WDTCON_16s // WDT on, timeout 16 s 128 #define setWDTon_32s() _WDTCON = WDTCON_32s // WDT on, timeout 32 s 129 #define setWDTon_64s() _WDTCON = WDTCON_64s // WDT on, timeout 64 s 130 #define setWDTon_128s() _WDTCON = WDTCON_128s // WDT on, timeout 128 s 131 #define setWDTon_256s() _WDTCON = WDTCON_256s // WDT on, timeout 256 s 132 133 // --- Debug with breakpoint number --- 134 // uns8 wValue: breakpoint number displayed in IQRF IDE 135 #define debugW(wValue) \ 136 do { \ 137 W = wValue; \ 138 debug(); \ 139 } while (0) 140 141 #define breakpoint(wValue) debugW(wValue) 142 143 // --- Brown-Out Reset --- 144 #if defined TR7xD 145 #define setBORon() writeToRAM(&BORCON, 0x80) // BOR on 146 #define setBORoff() writeToRAM(&BORCON, 0x00) // BOR off 147 #else 148 #define setBORon() BORCON = 0x80 // BOR on 149 #define setBORoff() BORCON = 0x00 // BOR off 150 #endif 151 152 // --- setupRFPGM(parameter) --- 153 #define _DUAL_CHANNEL 0x03 // RFPGM dual channel receiving 154 #define _LP_MODE 0x04 // RFPGM low power mode receiving 155 #define _ENABLE_ON_RESET 0x10 // RFPGM invoking by reset 156 #define _TIME_TERMINATE 0x40 // RFPGM auto termination after ~1 min 157 #define _PIN_TERMINATE 0x80 // RFPGM termination by MCU pins 158 159 // --- external EEPROM & temperature sensor power control --- 160 #define eEEPROM_TempSensorOn() _PWRT = 1 161 #define eEEPROM_TempSensorOff() _PWRT = 0 162 163 // --- Interrupt on change flags control --- 164 #define clearIOCF() IOCBF.4 = 0 // Clear interrupt on change flag. 165 #if defined TR7xD 166 #define clearIOCBN() writeToRAM(&IOCBN, IOCBN & ~0x10) // Clear negative edge flag. This bit (IOCBN.4) can not be accessed directly due to OS restriction. 167 #define setIOCBN() writeToRAM(&IOCBN, IOCBN | 0x10) // Negative edge active. This bit (IOCBN.4) can not be accessed directly due to OS restriction. 168 #else 169 #define clearIOCBN() IOCBN.4 = 0 // Clear negative edge flag. 170 #define setIOCBN() IOCBN.4 = 1 // Negative edge active. 171 #endif 172 173 // --- FRC Response time --- 174 #define _FRC_RESPONSE_TIME_40_MS 0b0.000.0000 // 40 ms 175 #define _FRC_RESPONSE_TIME_360_MS 0b0.001.0000 // 360 ms 176 #define _FRC_RESPONSE_TIME_680_MS 0b0.010.0000 // 680 ms 177 #define _FRC_RESPONSE_TIME_1320_MS 0b0.011.0000 // 1320 ms 178 #define _FRC_RESPONSE_TIME_2600_MS 0b0.100.0000 // 2600 ms 179 #define _FRC_RESPONSE_TIME_5160_MS 0b0.101.0000 // 5160 ms 180 #define _FRC_RESPONSE_TIME_10280_MS 0b0.110.0000 // 10280 ms 181 #define _FRC_RESPONSE_TIME_20520_MS 0b0.111.0000 // 20520 ms 182 183 // --- FRC offline mode to set before sendFRC() is called --- 184 #define _FRC_OFFLINE_MODE 0b0000.1.000 185 186 // Only value ORed from the predefined constants ( FRC_RESPONSE_TIME_??? and/or _FRC_OFFLINE_MODE ) above can be used as a parameter "params" 187 #define setFRCparams( params ) \ 188 do { \ 189 configFRC &= ~( _FRC_RESPONSE_TIME_20520_MS | _FRC_OFFLINE_MODE ); \ 190 configFRC |= ( ( params ) & ( _FRC_RESPONSE_TIME_20520_MS | _FRC_OFFLINE_MODE ) ); \ 191 } while (0) 192 193 #define getFRCparams() ( configFRC & ( _FRC_RESPONSE_TIME_20520_MS | _FRC_OFFLINE_MODE ) ) 194 195 // --- Copy Application data from EEPROM to bufferINFO --- 196 #define appInfo() eeReadData((__EEAPPINFO - __EESTART), 32) 197 198 // --- Write one byte to specified location in RAM --- 199 #define writeToRAM(address, value) \ 200 do { \ 201 FSR0=address; \ 202 setINDF0(value); \ 203 } while(0) 204 205 // --- Macros relating to setFSRs() function --- 206 #define setFSR01(fsr0, fsr1) setFSRs( (fsr0) + ( ((uns8)(fsr1)) << 4 ) ) 207 #define setFSR0(fsr0) setFSR01( fsr0, _FSR_NONE ) 208 #define setFSR1(fsr1) setFSR01( _FSR_NONE, fsr1 ) 209 210 #define _FSR_NONE 0x00 // Set FSR to no buffer 211 #define _FSR_NINFO 0x01 // Set FSR to networkInfo 212 #define _FSR_INFO 0x02 // Set FSR to bufferINFO 213 #define _FSR_COM 0x03 // Set FSR to bufferCOM 214 #define _FSR_AUX 0x04 // Set FSR to bufferAUX 215 #define _FSR_RF 0x05 // Set FSR to bufferRF 216 #define _FSR_ntwADDR 0x07 // Set FSR to ntwADDR (bank 11) 217 218 // --- Service channels --- 219 #define SERVICE_CHANNELS_COUNT 3 220 221 // --- LED control --- 222 #define toggleLEDR() \ 223 #warning Do not combine direct access to the LEDs with calling the IQRF OS LED functions. \ 224 do { _LEDR ^= 1; } while ( 0 ) 225 226 #define toggleLEDG() \ 227 #warning Do not combine direct access to the LEDs with calling the IQRF OS LED functions. \ 228 do { _LEDG ^= 1; } while ( 0 ) 229 230 // --- PPS control --- 231 #if defined TR7xG 232 #define unlockPPS() \ 233 do { \ 234 GIE = 0; \ 235 PPSLOCK = 0x55; \ 236 PPSLOCK = 0xAA; \ 237 PPSLOCKED = 0; \ 238 } while(0) 239 240 #define lockPPS() \ 241 do { \ 242 PPSLOCK = 0x55; \ 243 PPSLOCK = 0xAA; \ 244 PPSLOCKED = 1; \ 245 GIE = 1; \ 246 } while(0) 247 #endif 248 249 // --- Macros relating to registers that can not be written directly due to OS restriction --- 250 #if defined TR7xG 251 #define setADPCH(value) writeToRAM(&ADPCH, value) // ADPCH 252 #define setTX1STA(value) writeToRAM(&TX1STA, value) // TX1STA 253 #define setBAUD1CON(value) writeToRAM(&BAUD1CON, value) // BAUD1CON 254 #define setCCPTMRS0(value) writeToRAM(&CCPTMRS0, value) // CCPTMRS0 255 #endif 256 257 // *********************************************************************