1 // *****************************************************************************
    2 //                               IQRF OS memory                                *
    3 // *****************************************************************************
    4 // Intended for:
    5 //   HW: TR-72D, TR-76D, TR-77D, TR-78D, TR-75D
    6 //   OS: v4.03D
    7 //
    8 // Online IQRF OS Reference Guide: http://www.iqrf.org/IQRF-OS-Reference-guide/
    9 //
   10 // Copyright (c) IQRF Tech s.r.o.
   11 //
   12 // File:    IQRF-memory.h
   13 // Version: v1.00                                   Revision: 15/03/2018
   14 //
   15 // Revision history:
   16 //   v1.00: 15/03/2018  First release for OS 4.03D.
   17 //
   18 // *****************************************************************************
   19 
   20 //******************************************************************************
   21 // Temperature sensor configuration registers 
   22 //******************************************************************************
   23 typedef struct                                      // Default setting: 0b0000.0100
   24 {
   25     bit resolution0;
   26     bit resolution1;
   27     bit powerDownMode;
   28     bit skipSetup;
   29 } TmpCfg;                                           // For internal usage only
   30 
   31 // *****************************************************************************
   32 uns8  usedBank0[80]     @ 0x020;                    // Do not use this space
   33 uns8  usedBank1[80]     @ 0x0A0;                    // Do not use this space
   34 uns8  usedBank2[80]     @ 0x120;                    // Do not use this space
   35 uns8  usedBank3[80]     @ 0x1A0;                    // Do not use this space
   36 uns8  usedBank4[80]     @ 0x220;                    // Do not use this space
   37 uns8  usedBank5[80]     @ 0x2A0;                    // Do not use this space
   38 uns8  usedBank6[80]     @ 0x320;                    // Do not use this space
   39 uns8  usedBank7[80]     @ 0x3A0;                    // Do not use this space
   40 uns8  usedBank8[80]     @ 0x420;                    // Do not use this space
   41 uns8  usedBank9[80]     @ 0x4A0;                    // Do not use this space
   42 uns8  usedBank10[80]    @ 0x520;                    // Do not use this space
   43 uns8  usedBank11[32]    @ 0x5A0;                    // Do not use 32B of bank11 (0x5A0 - 0x5BF)
   44 // user space: bank11 48B (0x5C0 - 0x5EF) , bank12: 48B (0x620 - 0x64F)
   45 #define UserBank_01     11
   46 #define UserBank_02     12
   47 
   48 //******************************************************************************
   49 // Dedicated buffers and file registers
   50 //******************************************************************************
   51 uns8    bufferINFO[64]  @ usedBank6;                // Auxiliary buffer, 64B long
   52 uns8    bufferCOM[64]   @ usedBank7;                // Buffer for communication routines, 64B long
   53 uns8    bufferAUX[64]   @ usedBank8;                // Auxiliary buffer, 64B long
   54 uns8    bufferRF[64]    @ usedBank9;                // Buffer for RF routines, 64B long
   55 
   56 uns8    X70[16]         @ 0x70;                     // Register array in shared bank for user application
   57 uns8    userReg0        @ X70;                      // User's register in all banks
   58 uns8    userReg1        @ X70[1];                   // User's register in all banks
   59 uns8    RFmodeByte      @ X70[2];                   // Current RF mode !!! Read Only !!!
   60 uns8    param2          @ X70[3];                   // Parameter_01 for function calls
   61 uns16   param3          @ X70[4];                   // Used as parameter for function calls
   62 uns16   param4          @ X70[6];                   // Used as parameter for function calls
   63 uns8    bitmapBitMask   @ X70[12];                  // Bit mask from addressBitmap function
   64 uns8    bitmapByteIndex @ X70[14];                  // Byte index from addressBitmap function
   65 uns8    userInterface   @ X70[15];                  // See below !!! Read Only !!!  
   66 
   67 // Network params !!! Read Only !!!
   68 bank11 uns8  ntwADDR            @ usedBank11[0x00]; // Network address
   69 bank11 uns8  ntwVRN             @ usedBank11[0x01]; // VRN
   70 bank11 uns8  ntwZIN             @ usedBank11[0x02]; // Zone index
   71 bank11 uns8  ntwDID             @ usedBank11[0x03]; // Discovery ID
   72 bank11 uns8  ntwPVRN            @ usedBank11[0x04]; // Parent VRN
   73 bank11 uns16 ntwUSERADDRESS     @ usedBank11[0x05]; // For internal usage only
   74 bank11 uns16 ntwID              @ usedBank11[0x07]; // Network identification (NID0/NID1)
   75 bank11 uns8  ntwVRNFNZ          @ usedBank11[0x09]; // For internal usage only
   76 bank11 uns8  ntwCFG             @ usedBank11[0x0A]; // Network configuration
   77 //
   78 bank11 uns8 memoryOffsetFrom    @ usedBank11[0x0B]; // Offset for copying buffers
   79 bank11 uns8 memoryOffsetTo      @ usedBank11[0x0C]; // Offset for copying buffers
   80 bank11 uns8 userStatus          @ usedBank11[0x0D]; // Register cleared by OS after power-on reset but not after other reset types
   81 bank11 uns8 toutRF              @ usedBank11[0x0E]; // Timeout for RFRXpacket duration
   82 bank11 uns8 RFspeed             @ usedBank11[0x0F]; // Current RF speed !!! Read Only !!!
   83 bank11 uns8 RFpower             @ usedBank11[0x10]; // Current RF power !!! Read Only !!!
   84 bank11 uns8 RFchannel           @ usedBank11[0x11]; // Current RF channel !!! Read Only !!!
   85 bank11 uns8 SPIpacketLength     @ usedBank11[0x12]; // SPI packet length !!! Read Only !!!
   86 bank11 uns8 lastRSSI            @ usedBank11[0x16]; // RSSI of last receipt !!! Read Only !!!
   87 bank11 uns8 configFRC           @ usedBank11[0x17]; // FRC configuration
   88 bank11 uns8 sysReg1             @ usedBank11[0x1B]; // System register
   89 //
   90 bank11 uns8 responseFRCvalue    @ usedBank11[0x1C]; // FRC response value for 2 bits or 1 byte FRC
   91 bank11 uns16 responseFRCvalue2B @ usedBank11[0x1C]; // Two bytes FRC response value
   92 bank11 uns32 responseFRCvalue4B @ usedBank11[0x1C]; // Four bytes FRC response value (use .low8, .low16, .high16, ... to access this variable at the free CC5X edition)
   93 //
   94 bank5 uns8 FRCextraTime         @ usedBank5[0x49];  // Additional waiting time [ticks] for FRC response
   95 bank5 uns8 bondingMask          @ usedBank5[0x4E];  // Bonding mask for remote bonding
   96 bank5 uns8 bondingCounter       @ usedBank5[0x4F];  // Bonding counter for remote bonding
   97 //
   98 bank3 TmpCfg tmpCfg             @ usedBank3[0x49];  // For internal usage only
   99 bank3 uns16 CRC16               @ usedBank3[0x4A];  // For internal usage only
  100 bank3 uns8 XLPticks             @ usedBank3[0x4C];  // Number of ticks remaining to end of XLP packet transmission
  101 bank3 uns8 memoryLimit          @ usedBank3[0x4D];  // Limit for copying buffers
  102 //
  103 bank0 uns8 sysReg2              @ usedBank0[0x22];  // System register
  104 //******************************************************************************
  105 // After getStatusSPI() in param2 there are information as below
  106 //******************************************************************************
  107 bit _SPIRX                      @ param2.3;         // Something received on SPI
  108 bit _SPICRCok                   @ param2.4;         // Received SPICRC (last one) was OK
  109 
  110 //******************************************************************************
  111 // After device reset in userReg0 there are information as below
  112 //******************************************************************************
  113 bit _BOR                        @ userReg0.0;       // Brown-out Reset flag
  114 bit _POR                        @ userReg0.1;       // Power-on Reset flag
  115 bit _RI                         @ userReg0.2;       // Reset Instruction Flag
  116 bit _PD                         @ userReg0.3;       // Power-down flag
  117 bit _TO                         @ userReg0.4;       // Watchdog time-out flag
  118 bit _RMCLR                      @ userReg0.5;       // MCLR Reset flag
  119 bit _STKUNF                     @ userReg0.6;       // Stack Underflow Reset flag
  120 bit _STKOVF                     @ userReg0.7;       // Stack Overflow Reset flag
  121 
  122 //******************************************************************************
  123 // ntwCFG register
  124 //******************************************************************************
  125 bit _disabledRouting            @ ntwCFG.2;         // Routing enabled/disabled !!! Read Only !!! 
  126 
  127 //******************************************************************************
  128 // userInterface register
  129 //******************************************************************************
  130 bit _enableUserInterrupt        @ userInterface.1;  // Enable user interrupt
  131 bit _wasFRC                     @ userInterface.2;  // FRC packet received !!! Read Only !!!
  132 bit _wasRouted                  @ userInterface.3;  // Packet was routed, same as wasRouted() !!! Read Only !!! 
  133 bit _916MHz                     @ userInterface.4;  // 916 MHz band selected !!! Read Only !!! 
  134 bit _filterCurrentNetwork       @ userInterface.5;  // Filtering on !!! Read Only !!! 
  135 bit _networkTwo                 @ userInterface.6;  // Network 2 selected !!! Read Only !!!
  136 bit _networkingMode             @ userInterface.7;  // Networking selected !!! Read Only !!!
  137 
  138 //******************************************************************************
  139 // System registers
  140 //******************************************************************************
  141 bit _systemLEDindication        @ sysReg1.2;        // Enable system LED indication
  142 bit _ignoreForcedRoutingLP      @ sysReg1.5;        // Disable Forced LP routing
  143 //
  144 bit _3CHTX                      @ sysReg2.1;        // TX using all 3 service channels
  145 bit _eeeError                   @ sysReg2.3;        // External EEPROM communication error indication
  146 bit _checkRFcfg_PQT             @ sysReg2.5;        // Enable preamble quality test for checkRF function
  147 
  148 //******************************************************************************
  149 // Registers dedicated to networking
  150 //******************************************************************************
  151 uns8 networkInfo[32]            @ usedBank5;
  152                         
  153 struct PINfield
  154 {                       
  155     bit                 AUXF1;
  156     bit                 AUXF0;
  157     bit                 SYSPF;
  158     bit                 DPAF;
  159     bit                 CRYPTF;
  160     bit                 ROUTEF;
  161     bit                 ACKF;
  162     bit                 NTWF;
  163 
  164 } PINF @ networkInfo;
  165 
  166 bit   _NTWF             @ PINF.NTWF;                // Networking packet requested
  167 bit   _ACKF             @ PINF.ACKF;                // Acknowledgment requested
  168 bit   _ROUTEF           @ PINF.ROUTEF;              // Routing requested
  169 bit   _CRYPTF           @ PINF.CRYPTF;              // Encryption requested
  170 bit   _DPAF             @ PINF.DPAF;                // DPA protocol requested
  171 bit   _SYSPF            @ PINF.SYSPF;               // System packet
  172 bit   _AUXF0            @ PINF.AUXF0;               // Reserved for future use
  173 bit   _AUXF1            @ PINF.AUXF1;               // Reserved for future use
  174 
  175 #define _NTWF_MASK      0b1000.0000
  176 #define _ACKF_MASK      0b0100.0000
  177 #define _ROUTEF_MASK    0b0010.0000
  178 #define _CRYPTF_MASK    0b0001.0000
  179 #define _DPAF_MASK      0b0000.1000
  180 #define _SYSPF_MASK     0b0000.0100
  181 #define _AUXF0_MASK     0b0000.0010
  182 #define _AUXF1_MASK     0b0000.0001
  183 
  184 uns8  PIN               @ networkInfo;              // Packet info
  185 uns8  DLEN              @ networkInfo[1];           // Data length in packet
  186 uns8  RX                @ networkInfo[3];           // Addressee of packet
  187 uns8  TX                @ networkInfo[4];           // Direct sender of packet
  188 uns8  PID               @ networkInfo[7];           // Packet identification
  189 uns8  RTOTX             @ networkInfo[8];           // Originated sender of packet
  190 uns8  RTDEF             @ networkInfo[9];           // Routing definition
  191 
  192 uns8  RTHOPS            @ networkInfo[10];          // Routing data 0 - number of hops
  193 uns8  RTTSLOT           @ networkInfo[11];          // Routing data 1 - timeslot length [tick]
  194 uns8  RTDID             @ networkInfo[12];          // Routing data 2 - Discovery ID (set by OS)
  195 uns8  RTAUX             @ networkInfo[13];          // Routing data 3 - H byte for 2 byte addressing
  196 
  197 uns8  PNUM              @ networkInfo[14];          // DPA - Peripheral number
  198 uns8  PCMD              @ networkInfo[15];          // DPA - Peripheral command
  199 uns8  PPAR              @ networkInfo[16];          // DPA - Peripheral parameter
  200 
  201 //******************************************************************************
  202 // Variables for bidirectional user data exchange and MID transfer during prebonding
  203 //******************************************************************************                                             
  204 
  205 // User data passed in/out during (pre)bonding.
  206 uns8 hostUserDataToSend[4]   @ bufferINFO[22];      // [C/N] > [N] before (pre)bonding function
  207 uns8 nodeUserDataToSend[4]   @ bufferINFO[22];      // [N] > [C/N] before (pre)bonding function
  208 uns8 hostUserDataReceived[4] @ bufferINFO[22];      // [C/N] > [N] after (pre)bonding function
  209 uns8 nodeUserDataReceived[4] @ bufferRF[6];         // [N] > [C/N] after (pre)bonding function
  210 
  211 uns8 BondingNodeMID[4]  @ bufferRF[0];              // MID of the bond requesting node in the received system packet, before optional call of prebondNode(), or
  212                                                     // MID of prebonded Node to be authorized by nodeAuthorization(address).
  213 
  214 //******************************************************************************
  215 // FRC variables
  216 //******************************************************************************
  217 // configFRC register
  218 bit _selectiveFRCmode               @ configFRC.0;      // Enables selective FRC
  219 bit _2ByteFRCmode                   @ configFRC.1;      // Enables two byte FRC
  220 bit _4ByteFRCmode                   @ configFRC.2;      // Enables four byte FRC
  221 bit _virtualFRCmode                 @ configFRC.7;      // Enables virtual FRC
  222 
  223 // Variables for bidirectional user data exchange during FRC
  224 uns8 DataInSendFRC[30]              @ bufferRF[32];     // User data passed with FRC, filled-in before calling sendFRC().
  225 uns8 DataOutBeforeResponseFRC[30]   @ bufferRF[32];     // User data obtained after FRC receiving, formerly passed via DataInSendFRC.
  226 
  227 bit _2ByteFRC                       @ bufferRF[30].1;   // Two byte FRC indicator on Node side
  228 bit _4ByteFRC                       @ bufferRF[30].2;   // Four byte FRC indicator on Node side
  229 bit _virtualFRC                     @ bufferRF[30].7;   // Virtual FRC indicator on Node side
  230 
  231 //******************************************************************************
  232 // TR module info
  233 //******************************************************************************
  234 // Module info structure available at bufferINFO after calling moduleInfo();
  235 typedef struct
  236 {
  237     uns8       MID[4];
  238     uns8       OsVersion;
  239     uns8       TrType;
  240     uns16      OsBuild;
  241 } TModuleInfo;
  242 
  243 TModuleInfo ModuleInfo @ bufferINFO;
  244 
  245 //******************************************************************************
  246 // Constants
  247 //******************************************************************************
  248 #define __EEESTART                      0x0200      // Virtual begin of external EEPROM
  249 
  250 #define __EESTART                       0xF000      // Begin of internal EEPROM
  251 #define __EEAPPINFO                     0xF0A0      // EEPROM user's application data, 32B
  252 
  253 #define __EXTENDED_FLASH                0x2C00      // Begin of extended Flash memory
  254 #define __LICENSED_FLASH                __EXTENDED_FLASH
  255 #define __EXTENDED_FLASH_NEXT_PAGE      0x3000      // Next page of extended Flash memory
  256 #define __LICENSED_FLASH_NEXT_PAGE      __EXTENDED_FLASH_NEXT_PAGE
  257 #define __MAX_LICENSED_FLASH_ADDRESS    0x37BF      // Maximum address at licensed Flash memory
  258 #define __USER_INTERRUPT                0x3F00      // User interrupt address
  259 #define __MAX_FLASH_ADDRESS             0x3FFF      // Maximum Flash memory address
  260 
  261 #ifndef __APPLICATION_ADDRESS
  262 #define __APPLICATION_ADDRESS           0x3A00      // Begin of user application Flash memory
  263 #endif
  264 
  265 #define __FRCOMMAND                     0x0D        // FRC command
  266 #define __FRCOMMANDADV                  0x0C        // Advanced FRC command
  267 
  268 //******************************************************************************
  269 // I/O definitions
  270 //******************************************************************************
  271     #define _SDO        LATC.5                      // SPI SDO (output)
  272     #define _SDI        PORTC.4                     // SPI SDI (input)
  273     #define _SCK        PORTC.3                     // SPI SCK (input)
  274     #define _SS         PORTA.5                     // SPI SS (input)
  275     #define _LEDR       LATA.2                      // Red LED (output)
  276     #define _LEDG       LATB.7                      // Green LED (output)
  277     #define _PWRT       PORTA.3                     // Ext. EEPROM & temper. sensor supply voltage control (output)
  278     
  279 #if defined TR72D
  280     #define _C1_IN      PORTA.0                     // C1 as input
  281     #define _C1_OUT     LATA.0                      // C1 as output
  282     #define _C1_TRIS    TRISA.0                     // C1 direction
  283     
  284     #define _C2_IN      PORTC.2                     // C2 as input
  285     #define _C2_OUT     LATC.2                      // C2 as output
  286     #define _C2_TRIS    TRISC.2                     // C2 direction
  287     
  288     #define _C5_IN      PORTA.5                     // C5 (SS) as input
  289     #define _C5_OUT     LATA.5                      // C5 (SS) as output
  290     #define _C5_TRIS    TRISA.5                     // C5 (SS) direction
  291 
  292     #define _C6_IN      PORTC.3                     // C6 (SCK) as input
  293     #define _C6_OUT     LATC.3                      // C6 (SCK) as output
  294     #define _C6_TRIS    TRISC.3                     // C6 (SCK) direction
  295   
  296     #define _C7_IN      PORTC.4                     // C7 (SDI) as input
  297     #define _C7_OUT     LATC.4                      // C7 (SDI) as output
  298     #define _C7_TRIS    TRISC.4                     // C7 (SDI) direction
  299 
  300     #define _C8_IN      PORTC.5                     // C8 (SDO) as input
  301     #define _C8_OUT     LATC.5                      // C8 (SDO) as output
  302     #define _C8_TRIS    TRISC.5                     // C8 (SDO) direction
  303     
  304 #elif defined TR76D || defined TR77D
  305     #define _WAKEUP     PORTB.4                     // Wake-up (Q12) (input)
  306     
  307     #define _Q4_IN      PORTC.6                     // Q4 as input
  308     #define _Q4_OUT     LATC.6                      // Q4 as output
  309     #define _Q4_TRIS    TRISC.6                     // Q4 direction
  310     
  311     #define _Q5_IN      PORTC.7                     // Q5 as input
  312     #define _Q5_OUT     LATC.7                      // Q5 as output
  313     #define _Q5_TRIS    TRISC.7                     // Q5 direction
  314     
  315     #define _Q6_IN      PORTC.3                     // Q6 (SCK) as input
  316     #define _Q6_OUT     LATC.3                      // Q6 (SCK) as output
  317     #define _Q6_TRIS    TRISC.3                     // Q6 (SCK) direction 
  318     
  319     #define _Q7_IN      PORTC.4                     // Q7 (SDI) as input
  320     #define _Q7_OUT     LATC.4                      // Q7 (SDI) as output
  321     #define _Q7_TRIS    TRISC.4                     // Q7 (SDI) direction 
  322     
  323     #define _Q8_IN      PORTC.5                     // Q8 (SDO) as input
  324     #define _Q8_OUT     LATC.5                      // Q8 (SDO) as output
  325     #define _Q8_TRIS    TRISC.5                     // Q8 (SDO) direction 
  326             
  327     #define _Q9_IN      PORTA.5                     // Q9 (SS) as input
  328     #define _Q9_OUT     LATA.5                      // Q9 (SS) as output
  329     #define _Q9_TRIS    TRISA.5                     // Q9 (SS) direction 
  330     
  331     #define _Q10_IN     PORTB.7                     // Q10 (LEDG) as input
  332     #define _Q10_OUT    LATB.7                      // Q10 (LEDG) as output
  333     #define _Q10_TRIS   TRISB.7                     // Q10 (LEDG) direction 
  334     
  335     #define _Q11_IN     PORTA.2                     // Q11 (LEDR) as input
  336     #define _Q11_OUT    LATA.2                      // Q11 (LEDR) as output
  337     #define _Q11_TRIS   TRISA.2                     // Q11 (LEDR) direction 
  338     
  339     #define _Q12_IN     PORTB.4                     // Q12 (wake-up) as input
  340     #define _Q12_OUT    LATB.4                      // Q12 (wake-up) as output
  341     #define _Q12_TRIS   TRISB.4                     // Q12 (wake-up) direction 
  342     
  343     #define _Q13_IN     PORTE.3                     // Q13 as input (input only)
  344     #define _Q13_TRIS   TRISE.3                     // Q13 direction 
  345 
  346     #define _Q14_IN     PORTA.0                     // Q14 as input
  347     #define _Q14_OUT    LATA.0                      // Q14 as output
  348     #define _Q14_TRIS   TRISA.0                     // Q14 direction 
  349     
  350     #define _Q15_IN     PORTC.2                     // Q15 as input
  351     #define _Q15_OUT    LATC.2                      // Q15 as output
  352     #define _Q15_TRIS   TRISC.2                     // Q15 direction
  353 
  354 #elif defined TR78D
  355     #define _Q3_IN      PORTC.4                     // Q3 (SDI) as input
  356     #define _Q3_OUT     LATC.4                      // Q3 (SDI) as output
  357     #define _Q3_TRIS    TRISC.4                     // Q3 (SDI) direction
  358 
  359     #define _Q4_IN      PORTC.5                     // Q4 (SDO) as input
  360     #define _Q4_OUT     LATC.5                      // Q4 (SDO) as output
  361     #define _Q4_TRIS    TRISC.5                     // Q4 (SDO) direction
  362     
  363     #define _Q5_IN      PORTA.5                     // Q5 (SS) as input
  364     #define _Q5_OUT     LATA.5                      // Q5 (SS) as output
  365     #define _Q5_TRIS    TRISA.5                     // Q5 (SS) direction
  366 
  367     #define _Q6_IN      PORTC.3                     // Q6 (SCK) as input
  368     #define _Q6_OUT     LATC.3                      // Q6 (SCK) as output
  369     #define _Q6_TRIS    TRISC.3                     // Q6 (SCK) direction
  370 
  371 #elif defined TR75D
  372     #define _WAKEUP     PORTB.4                     // Wake-up (Q2) (input)
  373     
  374     #define _Q2_IN      PORTB.4                     // Q2 (wake-up) as input
  375     #define _Q2_OUT     LATB.4                      // Q2 (wake-up) as output
  376     #define _Q2_TRIS    TRISB.4                     // Q2 (wake-up) direction 
  377     
  378     #define _Q3_IN      PORTA.5                     // Q3 (SS) as input
  379     #define _Q3_OUT     LATA.5                      // Q3 (SS) as output
  380     #define _Q3_TRIS    TRISA.5                     // Q3 (SS) direction 
  381     
  382     #define _Q4_IN      PORTC.5                     // Q4 (SDO) as input
  383     #define _Q4_OUT     LATC.5                      // Q4 (SDO) as output
  384     #define _Q4_TRIS    TRISC.5                     // Q4 (SDO) direction
  385     
  386     #define _Q5_IN      PORTC.4                     // Q5 (SDI) as input
  387     #define _Q5_OUT     LATC.4                      // Q5 (SDI) as output
  388     #define _Q5_TRIS    TRISC.4                     // Q5 (SDI) direction
  389     
  390     #define _Q6_IN      PORTC.3                     // Q6 (SCK) as input
  391     #define _Q6_OUT     LATC.3                      // Q6 (SCK) as output
  392     #define _Q6_TRIS    TRISC.3                     // Q6 (SCK) direction 
  393     
  394     #define _Q8_IN      PORTE.3                     // Q8 as input (input only)
  395     #define _Q8_TRIS    TRISE.3                     // Q8 direction 
  396 
  397     #define _Q9_IN      PORTA.0                     // Q9 as input
  398     #define _Q9_OUT     LATA.0                      // Q9 as output
  399     #define _Q9_TRIS    TRISA.0                     // Q9 direction 
  400     
  401     #define _Q10_IN     PORTC.2                     // Q10 as input
  402     #define _Q10_OUT    LATC.2                      // Q10 as output
  403     #define _Q10_TRIS   TRISC.2                     // Q10 direction
  404     
  405     #define _Q11_IN     PORTC.7                     // Q11 as input
  406     #define _Q11_OUT    LATC.7                      // Q11 as output
  407     #define _Q11_TRIS   TRISC.7                     // Q11 direction
  408     
  409     #define _Q12_IN     PORTC.6                     // Q12 as input
  410     #define _Q12_OUT    LATC.6                      // Q12 as output
  411     #define _Q12_TRIS   TRISC.6                     // Q12 direction
  412     
  413 #else
  414     #error IQRF-memory.h does not correspond to selected TR module type.
  415 #endif
  416 //******************************************************************************
  417 #pragma rambank = UserBank_01                       // User's registers will be allocated in bank11