1 // ***************************************************************************** 2 // IQRF OS memory * 3 // ***************************************************************************** 4 // Intended for: 5 // HW: TR-72D, TR-76D, TR-77D, TR-78D, TR-75D 6 // OS: v4.02D 7 // 8 // Online IQRF OS Reference Guide: http://www.iqrf.org/IQRF-OS-Reference-guide/ 9 // 10 // Copyright (c) IQRF Tech s.r.o. 11 // 12 // File: IQRF-memory.h 13 // Version: v1.01 Revision: 02/10/2017 14 // 15 // Revision history: 16 // v1.01: 02/10/2017 TR-75D supported. 17 // v1.00: 22/08/2017 First release for OS 4.02D. 18 // 19 // ***************************************************************************** 20 21 //****************************************************************************** 22 // Temperature sensor configuration registers 23 //****************************************************************************** 24 typedef struct // Default setting: 0b0000.0100 25 { 26 bit resolution0; 27 bit resolution1; 28 bit powerDownMode; 29 bit skipSetup; 30 } TmpCfg; // For internal usage only 31 32 // ***************************************************************************** 33 uns8 usedBank0[80] @ 0x020; // Do not use this space 34 uns8 usedBank1[80] @ 0x0A0; // Do not use this space 35 uns8 usedBank2[80] @ 0x120; // Do not use this space 36 uns8 usedBank3[80] @ 0x1A0; // Do not use this space 37 uns8 usedBank4[80] @ 0x220; // Do not use this space 38 uns8 usedBank5[80] @ 0x2A0; // Do not use this space 39 uns8 usedBank6[80] @ 0x320; // Do not use this space 40 uns8 usedBank7[80] @ 0x3A0; // Do not use this space 41 uns8 usedBank8[80] @ 0x420; // Do not use this space 42 uns8 usedBank9[80] @ 0x4A0; // Do not use this space 43 uns8 usedBank10[80] @ 0x520; // Do not use this space 44 uns8 usedBank11[32] @ 0x5A0; // Do not use 32B of bank11 (0x5A0 - 0x5BF) 45 // user space: bank11 48B (0x5C0 - 0x5EF) , bank12: 48B (0x620 - 0x64F) 46 #define UserBank_01 11 47 #define UserBank_02 12 48 49 //****************************************************************************** 50 // Dedicated buffers and file registers 51 //****************************************************************************** 52 uns8 bufferINFO[64] @ usedBank6; // Auxiliary buffer, 64B long 53 uns8 bufferCOM[64] @ usedBank7; // Buffer for communication routines, 64B long 54 uns8 bufferAUX[64] @ usedBank8; // Auxiliary buffer, 64B long 55 uns8 bufferRF[64] @ usedBank9; // Buffer for RF routines, 64B long 56 57 uns8 X70[16] @ 0x70; // Register array in shared bank for user application 58 uns8 userReg0 @ X70; // User's register in all banks 59 uns8 userReg1 @ X70[1]; // User's register in all banks 60 uns8 RFmodeByte @ X70[2]; // Current RF mode !!! Read Only !!! 61 uns8 param2 @ X70[3]; // Parameter_01 for function calls 62 uns16 param3 @ X70[4]; // Used as parameter for function calls 63 uns16 param4 @ X70[6]; // Used as parameter for function calls 64 uns8 userInterface @ X70[15]; // See below !!! Read Only !!! 65 66 // Network params !!! Read Only !!! 67 bank11 uns8 ntwADDR @ usedBank11[0x00]; // Network address 68 bank11 uns8 ntwVRN @ usedBank11[0x01]; // VRN 69 bank11 uns8 ntwZIN @ usedBank11[0x02]; // Zone index 70 bank11 uns8 ntwDID @ usedBank11[0x03]; // Discovery ID 71 bank11 uns8 ntwPVRN @ usedBank11[0x04]; // Parent VRN 72 bank11 uns16 ntwUSERADDRESS @ usedBank11[0x05]; // User address 2B 73 bank11 uns16 ntwID @ usedBank11[0x07]; // Network identification (NID0/NID1) 74 bank11 uns8 ntwVRNFNZ @ usedBank11[0x09]; // VRN of first Node in given zone 75 bank11 uns8 ntwCFG @ usedBank11[0x0A]; // Network configuration 76 // 77 bank11 uns8 memoryOffsetFrom @ usedBank11[0x0B]; // Offset for copying buffers 78 bank11 uns8 memoryOffsetTo @ usedBank11[0x0C]; // Offset for copying buffers 79 bank11 uns8 userStatus @ usedBank11[0x0D]; // Register cleared by OS after power-on reset but not after other reset types 80 bank11 uns8 toutRF @ usedBank11[0x0E]; // Timeout for RFRXpacket duration 81 bank11 uns8 RFspeed @ usedBank11[0x0F]; // Current RF speed !!! Read Only !!! 82 bank11 uns8 RFpower @ usedBank11[0x10]; // Current RF power !!! Read Only !!! 83 bank11 uns8 RFchannel @ usedBank11[0x11]; // Current RF channel !!! Read Only !!! 84 bank11 uns8 SPIpacketLength @ usedBank11[0x12]; // SPI packet length !!! Read Only !!! 85 bank11 uns8 lastRSSI @ usedBank11[0x16]; // RSSI of last receipt !!! Read Only !!! 86 bank11 uns8 configFRC @ usedBank11[0x17]; // FRC configuration 87 bank11 uns8 responseFRCvalue @ usedBank11[0x18]; // FRC response user value 88 bank11 uns16 responseFRCvalue2B @ usedBank11[0x19]; // Two bytes FRC response user value 89 bank11 uns8 sysReg1 @ usedBank11[0x1B]; // System register 90 // 91 bank5 uns8 FRCextraTime @ usedBank5[0x49]; // Additional waiting time [ticks] for FRC response 92 bank5 uns8 bondingMask @ usedBank5[0x4E]; // Bonding mask for remote bonding 93 bank5 uns8 bondingCounter @ usedBank5[0x4F]; // Bonding counter for remote bonding 94 // 95 bank3 TmpCfg tmpCfg @ usedBank3[0x49]; // For internal usage only 96 bank3 uns16 CRC16 @ usedBank3[0x4A]; // For internal usage only 97 bank3 uns8 XLPticks @ usedBank3[0x4C]; // Number of ticks remaining to end of XLP packet transmission 98 bank3 uns8 memoryLimit @ usedBank3[0x4D]; // Limit for copying buffers 99 // 100 bank0 uns8 sysReg2 @ usedBank0[0x22]; // System register 101 //****************************************************************************** 102 // After getStatusSPI() in param2 there are information as below 103 //****************************************************************************** 104 bit _SPIRX @ param2.3; // Something received on SPI 105 bit _SPICRCok @ param2.4; // Received SPICRC (last one) was OK 106 107 //****************************************************************************** 108 // After device reset in userReg0 there are information as below 109 //****************************************************************************** 110 bit _BOR @ userReg0.0; // Brown-out Reset flag 111 bit _POR @ userReg0.1; // Power-on Reset flag 112 bit _RI @ userReg0.2; // Reset Instruction Flag 113 bit _PD @ userReg0.3; // Power-down flag 114 bit _TO @ userReg0.4; // Watchdog time-out flag 115 bit _RMCLR @ userReg0.5; // MCLR Reset flag 116 bit _STKUNF @ userReg0.6; // Stack Underflow Reset flag 117 bit _STKOVF @ userReg0.7; // Stack Overflow Reset flag 118 119 //****************************************************************************** 120 // ntwCFG register 121 //****************************************************************************** 122 bit _disabledRouting @ ntwCFG.2; // Routing enabled/disabled !!! Read Only !!! 123 124 //****************************************************************************** 125 // userInterface register 126 //****************************************************************************** 127 bit _enableUserInterrupt @ userInterface.1; // Enable user interrupt 128 bit _wasFRC @ userInterface.2; // FRC packet received !!! Read Only !!! 129 bit _wasRouted @ userInterface.3; // Packet was routed, same as wasRouted() !!! Read Only !!! 130 bit _916MHz @ userInterface.4; // 916 MHz band selected !!! Read Only !!! 131 bit _filterCurrentNetwork @ userInterface.5; // Filtering on !!! Read Only !!! 132 bit _networkTwo @ userInterface.6; // Network 2 selected !!! Read Only !!! 133 bit _networkingMode @ userInterface.7; // Networking selected !!! Read Only !!! 134 135 //****************************************************************************** 136 // System registers 137 //****************************************************************************** 138 bit _systemLEDindication @ sysReg1.2; // Enable system LED indication 139 bit _ignoreForcedRoutingLP @ sysReg1.5; // Disable Forced LP routing 140 bit _advancedFRCmode @ sysReg1.6; // Enable Advanced FRC mode 141 // 142 bit _eeeError @ sysReg2.3; // External EEPROM communication error indication 143 bit _checkRFcfg_PQT @ sysReg2.5; // Enable preamble quality test for checkRF function 144 145 //****************************************************************************** 146 // Registers dedicated to networking 147 //****************************************************************************** 148 uns8 networkInfo[32] @ usedBank5; 149 150 struct PINfield 151 { 152 bit AUXF1; 153 bit AUXF0; 154 bit SYSPF; 155 bit DPAF; 156 bit CRYPTF; 157 bit ROUTEF; 158 bit ACKF; 159 bit NTWF; 160 161 } PINF @ networkInfo; 162 163 bit _NTWF @ PINF.NTWF; // Networking packet requested 164 bit _ACKF @ PINF.ACKF; // Acknowledgment requested 165 bit _ROUTEF @ PINF.ROUTEF; // Routing requested 166 bit _CRYPTF @ PINF.CRYPTF; // Encryption requested 167 bit _DPAF @ PINF.DPAF; // DPA protocol requested 168 bit _SYSPF @ PINF.SYSPF; // System packet 169 bit _AUXF0 @ PINF.AUXF0; // Reserved for future use 170 bit _AUXF1 @ PINF.AUXF1; // Reserved for future use 171 172 #define _NTWF_MASK 0b1000.0000 173 #define _ACKF_MASK 0b0100.0000 174 #define _ROUTEF_MASK 0b0010.0000 175 #define _CRYPTF_MASK 0b0001.0000 176 #define _DPAF_MASK 0b0000.1000 177 #define _SYSPF_MASK 0b0000.0100 178 #define _AUXF0_MASK 0b0000.0010 179 #define _AUXF1_MASK 0b0000.0001 180 181 uns8 PIN @ networkInfo; // Packet info 182 uns8 DLEN @ networkInfo[1]; // Data length in packet 183 uns8 RX @ networkInfo[3]; // Addressee of packet 184 uns8 TX @ networkInfo[4]; // Direct sender of packet 185 uns8 PID @ networkInfo[7]; // Packet identification 186 uns8 RTOTX @ networkInfo[8]; // Originated sender of packet 187 uns8 RTDEF @ networkInfo[9]; // Routing definition 188 189 uns8 RTHOPS @ networkInfo[10]; // Routing data 0 - number of hops 190 uns8 RTTSLOT @ networkInfo[11]; // Routing data 1 - timeslot length [tick] 191 uns8 RTDID @ networkInfo[12]; // Routing data 2 - Discovery ID (set by OS) 192 uns8 RTAUX @ networkInfo[13]; // Routing data 3 - H byte for 2 byte addressing 193 194 uns8 PNUM @ networkInfo[14]; // DPA - Peripheral number 195 uns8 PCMD @ networkInfo[15]; // DPA - Peripheral command 196 uns8 PPAR @ networkInfo[16]; // DPA - Peripheral parameter 197 198 //****************************************************************************** 199 // Variables for bidirectional user data exchange and MID transfer during prebonding 200 //****************************************************************************** 201 uns8 UserBondingData[4] @ bufferRF[6]; // User data passed in/out during (pre)bonding. 202 uns8 BondingNodeMID[4] @ bufferRF[0]; // MID of the bond requesting node in the received system packet, before optional call of prebondNode(), or 203 // MID of prebonded Node to be authorized by nodeAuthorization(address). 204 205 //****************************************************************************** 206 // FRC variables 207 //****************************************************************************** 208 // configFRC register 209 bit _selectiveFRCmode @ configFRC.0; // Enable selective FRC 210 bit _twoByteFRCmode @ configFRC.1; // Enable two byte FRC 211 212 // Variables for bidirectional user data exchange during FRC 213 uns8 DataInSendFRC[30] @ bufferRF[32]; // User data passed with FRC, filled-in before calling sendFRC(). 214 uns8 DataOutBeforeResponseFRC[30] @ bufferRF[32]; // User data obtained after FRC receiving, formerly passed via DataInSendFRC. 215 216 bit _twoByteFRC @ bufferRF[30].1; // Two byte FRC indicator on Node side 217 218 //****************************************************************************** 219 // Constants 220 //****************************************************************************** 221 #define __EEESTART 0x0200 // Virtual begin of external EEPROM 222 223 #define __EESTART 0xF000 // Begin of internal EEPROM 224 #define __EEAPPINFO 0xF0A0 // EEPROM user's application data, 32B 225 226 #define __EXTENDED_FLASH 0x2C00 // Begin of extended Flash memory 227 #define __LICENSED_FLASH __EXTENDED_FLASH 228 #define __EXTENDED_FLASH_NEXT_PAGE 0x3000 // Next page of extended Flash memory 229 #define __LICENSED_FLASH_NEXT_PAGE __EXTENDED_FLASH_NEXT_PAGE 230 #define __MAX_LICENSED_FLASH_ADDRESS 0x37BF // Maximum address at licensed Flash memory 231 #define __USER_INTERRUPT 0x3F00 // User interrupt address 232 #define __MAX_FLASH_ADDRESS 0x3FFF // Maximum Flash memory address 233 234 #ifndef __APPLICATION_ADDRESS 235 #define __APPLICATION_ADDRESS 0x3A00 // Begin of user application Flash memory 236 #endif 237 238 #define __FRCOMMAND 0x0D // FRC command 239 #define __FRCOMMANDADV 0x0C // Advanced FRC command 240 241 //****************************************************************************** 242 // I/O definitions 243 //****************************************************************************** 244 #define _SDO LATC.5 // SPI SDO (output) 245 #define _SDI PORTC.4 // SPI SDI (input) 246 #define _SCK PORTC.3 // SPI SCK (input) 247 #define _SS PORTA.5 // SPI SS (input) 248 #define _LEDR LATA.2 // Red LED (output) 249 #define _LEDG LATB.7 // Green LED (output) 250 #define _PWRT PORTA.3 // Ext. EEPROM & temper. sensor supply voltage control (output) 251 252 #if defined TR72D 253 #define _C1_IN PORTA.0 // C1 as input 254 #define _C1_OUT LATA.0 // C1 as output 255 #define _C1_TRIS TRISA.0 // C1 direction 256 257 #define _C2_IN PORTC.2 // C2 as input 258 #define _C2_OUT LATC.2 // C2 as output 259 #define _C2_TRIS TRISC.2 // C2 direction 260 261 #define _C5_IN PORTA.5 // C5 (SS) as input 262 #define _C5_OUT LATA.5 // C5 (SS) as output 263 #define _C5_TRIS TRISA.5 // C5 (SS) direction 264 265 #define _C6_IN PORTC.3 // C6 (SCK) as input 266 #define _C6_OUT LATC.3 // C6 (SCK) as output 267 #define _C6_TRIS TRISC.3 // C6 (SCK) direction 268 269 #define _C7_IN PORTC.4 // C7 (SDI) as input 270 #define _C7_OUT LATC.4 // C7 (SDI) as output 271 #define _C7_TRIS TRISC.4 // C7 (SDI) direction 272 273 #define _C8_IN PORTC.5 // C8 (SDO) as input 274 #define _C8_OUT LATC.5 // C8 (SDO) as output 275 #define _C8_TRIS TRISC.5 // C8 (SDO) direction 276 277 #elif defined TR76D || defined TR77D 278 #define _WAKEUP PORTB.4 // Wake-up (Q12) (input) 279 280 #define _Q4_IN PORTC.6 // Q4 as input 281 #define _Q4_OUT LATC.6 // Q4 as output 282 #define _Q4_TRIS TRISC.6 // Q4 direction 283 284 #define _Q5_IN PORTC.7 // Q5 as input 285 #define _Q5_OUT LATC.7 // Q5 as output 286 #define _Q5_TRIS TRISC.7 // Q5 direction 287 288 #define _Q6_IN PORTC.3 // Q6 (SCK) as input 289 #define _Q6_OUT LATC.3 // Q6 (SCK) as output 290 #define _Q6_TRIS TRISC.3 // Q6 (SCK) direction 291 292 #define _Q7_IN PORTC.4 // Q7 (SDI) as input 293 #define _Q7_OUT LATC.4 // Q7 (SDI) as output 294 #define _Q7_TRIS TRISC.4 // Q7 (SDI) direction 295 296 #define _Q8_IN PORTC.5 // Q8 (SDO) as input 297 #define _Q8_OUT LATC.5 // Q8 (SDO) as output 298 #define _Q8_TRIS TRISC.5 // Q8 (SDO) direction 299 300 #define _Q9_IN PORTA.5 // Q9 (SS) as input 301 #define _Q9_OUT LATA.5 // Q9 (SS) as output 302 #define _Q9_TRIS TRISA.5 // Q9 (SS) direction 303 304 #define _Q10_IN PORTB.7 // Q10 (LEDG) as input 305 #define _Q10_OUT LATB.7 // Q10 (LEDG) as output 306 #define _Q10_TRIS TRISB.7 // Q10 (LEDG) direction 307 308 #define _Q11_IN PORTA.2 // Q11 (LEDR) as input 309 #define _Q11_OUT LATA.2 // Q11 (LEDR) as output 310 #define _Q11_TRIS TRISA.2 // Q11 (LEDR) direction 311 312 #define _Q12_IN PORTB.4 // Q12 (wake-up) as input 313 #define _Q12_OUT LATB.4 // Q12 (wake-up) as output 314 #define _Q12_TRIS TRISB.4 // Q12 (wake-up) direction 315 316 #define _Q13_IN PORTE.3 // Q13 as input (input only) 317 #define _Q13_TRIS TRISE.3 // Q13 direction 318 319 #define _Q14_IN PORTA.0 // Q14 as input 320 #define _Q14_OUT LATA.0 // Q14 as output 321 #define _Q14_TRIS TRISA.0 // Q14 direction 322 323 #define _Q15_IN PORTC.2 // Q15 as input 324 #define _Q15_OUT LATC.2 // Q15 as output 325 #define _Q15_TRIS TRISC.2 // Q15 direction 326 327 #elif defined TR78D 328 #define _Q3_IN PORTC.4 // Q3 (SDI) as input 329 #define _Q3_OUT LATC.4 // Q3 (SDI) as output 330 #define _Q3_TRIS TRISC.4 // Q3 (SDI) direction 331 332 #define _Q4_IN PORTC.5 // Q4 (SDO) as input 333 #define _Q4_OUT LATC.5 // Q4 (SDO) as output 334 #define _Q4_TRIS TRISC.5 // Q4 (SDO) direction 335 336 #define _Q5_IN PORTA.5 // Q5 (SS) as input 337 #define _Q5_OUT LATA.5 // Q5 (SS) as output 338 #define _Q5_TRIS TRISA.5 // Q5 (SS) direction 339 340 #define _Q6_IN PORTC.3 // Q6 (SCK) as input 341 #define _Q6_OUT LATC.3 // Q6 (SCK) as output 342 #define _Q6_TRIS TRISC.3 // Q6 (SCK) direction 343 344 #elif defined TR75D 345 #define _WAKEUP PORTB.4 // Wake-up (Q2) (input) 346 347 #define _Q2_IN PORTB.4 // Q2 (wake-up) as input 348 #define _Q2_OUT LATB.4 // Q2 (wake-up) as output 349 #define _Q2_TRIS TRISB.4 // Q2 (wake-up) direction 350 351 #define _Q3_IN PORTA.5 // Q3 (SS) as input 352 #define _Q3_OUT LATA.5 // Q3 (SS) as output 353 #define _Q3_TRIS TRISA.5 // Q3 (SS) direction 354 355 #define _Q4_IN PORTC.5 // Q4 (SDO) as input 356 #define _Q4_OUT LATC.5 // Q4 (SDO) as output 357 #define _Q4_TRIS TRISC.5 // Q4 (SDO) direction 358 359 #define _Q5_IN PORTC.4 // Q5 (SDI) as input 360 #define _Q5_OUT LATC.4 // Q5 (SDI) as output 361 #define _Q5_TRIS TRISC.4 // Q5 (SDI) direction 362 363 #define _Q6_IN PORTC.3 // Q6 (SCK) as input 364 #define _Q6_OUT LATC.3 // Q6 (SCK) as output 365 #define _Q6_TRIS TRISC.3 // Q6 (SCK) direction 366 367 #define _Q8_IN PORTE.3 // Q8 as input (input only) 368 #define _Q8_TRIS TRISE.3 // Q8 direction 369 370 #define _Q9_IN PORTA.0 // Q9 as input 371 #define _Q9_OUT LATA.0 // Q9 as output 372 #define _Q9_TRIS TRISA.0 // Q9 direction 373 374 #define _Q10_IN PORTC.2 // Q10 as input 375 #define _Q10_OUT LATC.2 // Q10 as output 376 #define _Q10_TRIS TRISC.2 // Q10 direction 377 378 #define _Q11_IN PORTC.7 // Q11 as input 379 #define _Q11_OUT LATC.7 // Q11 as output 380 #define _Q11_TRIS TRISC.7 // Q11 direction 381 382 #define _Q12_IN PORTC.6 // Q12 as input 383 #define _Q12_OUT LATC.6 // Q12 as output 384 #define _Q12_TRIS TRISC.6 // Q12 direction 385 386 #else 387 #error IQRF-memory.h does not correspond to selected TR module type. 388 #endif 389 //****************************************************************************** 390 #pragma rambank = UserBank_01 // User's registers will be allocated in bank11